The 10GBASE-X PCS provides services to the XGMII in a manner analogous to how the 1000BASE-X PCS provides services to the 1000 Mb/s GMII. 3-2008 standard and provides an interface between AHB/AXI Bus and the 10 Gigabit Media Independent Interface (XGMII) using a powerful 64-bit Scatter Gather DMA. As far as I understand, of those 72 pins, only 64 are actually data, the remai. 6. Serial-GMII Specification The Serial Gigabit Media Independent Interface (SGMII) is designed to satisfy the following requirements: • Convey network data and port speed between a 10/100/1000 PHY and a MAC with significantly less signal pins than required for GMII. At the Tampa meeting I intend to propose that we just adopt the logic family that the XGMII uses (we might have to put a note in about termination schemes as the MDIO is multi-drop). XAUI addresses several physical limitations of the XGMII. 3, Clause 47. 125Gbps for the XAUI interface. Media-Independent Interface（MII、媒体独立インタフェース）は、イーサネットにおいて、MAC (データリンク層デバイス)とPHY (物理層デバイス)とを接続するためのインタフェース。本稿では以下の拡張版を含めて記述する。 The XGMII interface defines the 32-bit data and 4-bit wide control character clocked between the MAC/RS and the PCS at both the positive and negative edge (double data rate – DDR) of the 156. After the 10 Gbps data is extracted from the four lanes, it must be formatted in a XGMII interface. A gigabit interface converter ( GBIC) is a standard for transceivers, first defined in 1995 and commonly used with Gigabit Ethernet and Fibre Channel for some time. These documents describe the technical characteristics of the antenna panels on the GPS Block IIR and Block IIR-M satellites. XGMII stands for X(roman 10)-G-Media-Independant-Interface which is IEEE 802. 125 Gbps at the PMD interface. Media Independent Interface ( MII )，介质独立接口，起初是定义100M以太网（Fast Ethernet）的 MAC 层与 PHY 芯片之间的传输标准（802. 3 Gbps, providing a maximum total aggregated data bandwidth of 8. PHY 8. 125Gbps 10GBASE-R Clause 49 (IEEE 64B/66B PCS only) o No IEEE Electrical Spec (no PMA) IEEE Specifications • 3. XGMII interface in my view will be short lived. This block contains the signals TXD (64. . Optional 802. 5M transfers/s) • PHY line rate is preserved (10. 8. 3125 Gb/s link. 10 Gigabit Media Independent Interface (XGMII) to the protocol device. "JUST" <smile>. Transceiver Status and Transceiver Clock Status Signals 6. ファイバーチャネル・オーバー・イーサネット. This specification, the Devicetree Specification (DTSpec), provides a complete boot program to client program interface definition, combined with minimum system requirements that facilitate the development of a wide variety of systems. The 10G USXGMII Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at 10M, 100M, 1G, 2. 7. g) Modified document formatting. There are a total of 28 pins within a cluster, so each cluster has enough signals to implement one GMII interface. MDI. My tests indicate the SOF marker for any received Ethernet frame seems to appear only as byte number 0 or 4 on the output, i. 44. MDI. GMII TBI verification IP is developed by experts in Ethernet, who have developed ethernet products in. 1. 3ae 10 Gigabit Ethernet Summary n The XGMII coding proposal is stable n The EIA/JEDEC SSTL_2 standard can be referenced for the XGMII electrical specification n The timing proposal presented herein is a starting point for further discussion 10-gigabit media-independent interface (XGMII) The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. Transport. 0. 1 XGMII Interface The XGMII interface connects the Reconciliation Sublayer (RS) with the IP and allows transferring information to/from as defined in Clause 46. This PHY IP core is made available as part of the transceiver functionality of the Intel® FPGAs. semi-formal notation to model SoS architectures with. Supports 10M, 100M, 1G, 2. Connection to the SerDes is through a configu-rable 16-, 20-, 32-, 40-, or 64-bit interface. 1. Section Content Features Release Information LL. 4. 3125 Gbps のシリアル シングル チャネルの PHY をインプリメントして、XFI 電気的仕様を使用した XFP への直接接続や、SFI 電気的仕様を使用した SFP+ オプティカル. Media-Independent Interface（MII、媒体独立インタフェース）は、イーサネットにおいて、MAC (データリンク層デバイス)とPHY (物理層デバイス)とを接続するためのインタフェース。本稿では以下の拡張版を含めて記述する。The XGMII interface defines the 32-bit data and 4-bit wide control character clocked between the MAC/RS and the PCS at both the positive and negative edge (double data rate – DDR) of the 156. September 23, 2021 Product Specification Rev1. Small Form-factor Pluggable (SFP) is a compact, hot-pluggable network interface module format used for both telecommunication and data communications applications. 3 that describe these levels allow voltages well above 5V, but I don't know of any 1. If anybody is interested to see this document please go to FC web site at and search for doc 99-251v3. Designed to Dune Networks RXAUI specification. 5 V MDIO I/O) RGMII. GMII Electrical Specification IEEE Interim Meeting, San Diego, January 1997 Dave Fifield 1-408-721-7937 fifield@lan. 1 Voltage Mode Line DriverCollection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). 7. Inter-Frame GAP. Transceiver Status and Transceiver Clock Status Signals 6. 3125 Gbit/s) • Data throughput is reduced: • inter-frame gaps are increased through extended operation of MPCP, which accounts for FEC parity insertion • Extra IDLEs are deleted in PCS and used to insert FEC partiyLow Power FPGAs. Simulation and verification. to the PCS synchronization specification. In this demo, the FiFo_wrapper_top module provides this interface. 3 Cat5 Twisted Pair Media Interface The VSC8514-11 twisted pair interface is compliant with IEEE802. (MAC), PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T PHY standard devices. Use Case ‘Front Light Management’: Exchange Type of Front Light. Interfaces. The most popular variant, 1000BASE-T, is defined by the IEEE 802. 0 > 2. ECU-Hardware. USGMII provides flexibility to add new features while maintaining backward compatibility. 5G/5G/10Gb Ethernet) PHY. Status Signals. As far as I understand, of those 72 pins, only 64 are actually data, the remai. Overview. 5G/1G Multi-Speed. 3-2018, Clause 46. 6. 5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core implements USXGMII PCS based on Cisco specification. 3. 2009 - 88X2040. This SGMII solution meets the SGMII specification and saves cost and power in systems that have low to high port-count Gigabit Ethernet per device. The IP core is compatible with the RGMII specification v2. All transmit data and control. Please refer to PG210. 2. Document Revision History for the F-Tile 1G/2. 3. The IEEE 802. Two XAUI link• Provide a physical layer specification supporting 100 Gb/s operation on a single wavelength capable of at least 80 km over a DWDM system. Transceiver Status and Transceiver Clock Status Signals 6. 3 media access control (MAC) and reconciliation sublayer (RS). Section Content. XGMII Signals 6. 3 protocol and MAC specification to an operating speedof 10 Gb/s. In the FPGA world where the MAC and PHY are implemented in the same chip technically this interface layer is not required, as the MAC and. (2) The XGMII extender sublayer (XGXS) extends the distance of XGMII when used with XUAI and provides the data conversion between XGMII and XAUI. The current generation of 10 Gigabit Ethernet components uses XGMII, another parallel interface designed for faster speeds. SerDes TX RX MII SerialThis solution is designed to the IEEE 802. On the opposite side a pair of XGMII interfaces are used to transfer frames between the nfmac10g and the PCS/PMA (or XAUI) core. 25MHz for direct interface to 10GBase-R, XAUI and RXUAI cores. (See IEEE Std 802. AUI – Attachment unit interface. PHY x. An XGMII interface for integration with the 10-Gigabit PHY; A GMII interface for integration with the 1-Gigabit PHY; The configurable XLGMAC IP is optimized for gate count and latency and offers a flexible RTL core for integration into a broad range of applications including network interface ports, backplane switches, and enterprise switches. The interface between the PCS and the RS is the XGMII as specified in Clause 46. In computer networking, Gigabit Ethernet ( GbE or 1 GigE) is the term applied to transmitting Ethernet frames at a rate of a gigabit per second. Reference HSTL at 1. Optional 802. I see three alternatives that would allow us to go forward to > TF ballot. Designed to meet the USXGMII specification EDCS-1467841 revision 1. XAUI uses four full-duplex serial links operating at 3. Statement on Forced Labor. 3125 Gbps). Figure 1. In total the interface is 74 bits wide. Introduction. About LL Ethernet 10G MAC 2. 16. Features. ) • 1. AMD provides a parameterizable LogiCORE™ IP solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system. 3 Clause 46, is the main access to the 10G Ethernet physical layer. 3u）。介质独立的意思是指，MAC与PHY之间的通信不受具体传输介质（双绞线或光纤等）的影响，任何MAC和PHY都可以通过MII接口互连。 MAC与PHY之间的MII连接可以是可插拔的连…Interface Avalon-ST XGMII/ GMII/MII 10M/100M/ LL 10GbE MAC PHY Serial Interface Note: Intel FPGAs implement and support the LL 10GbE Media Access Control (MAC) and Multi-Rate Ethernet PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T (1G/2. 3 standard. XGMII Mapping to Standard SDR XGMII Data. 1G/2. 3bz-2016 amending the XGMII specification to support operation at 2. e. Hi all , I'm using the zcu102 Ultrascale board for XGMII core with using PCS/PMA IP only. XGMII/GMII/RGMII: Source And Data Centered I/O Timing Modes; Supports Jumbo Packet (9600 byte maximum) Operation. 0 5 2. The PHY we have on the LS1046A RDB supports native XFI but sends PAUSE frames towards the MAC to regulate the lower speeds. 5GPII Implementation as shown does not require much incremental logic Does not preclude implementations that directly map XGMII into PCS Diagram above for IEEE functional specification purposes only 1000BASE-X PHY 2. Status Signals 6. interface. Return to the SSTL specifications of Draft 1. XGMII Update Page 12 of 12 hmf 11-July-2000 IEEE 802. It is important to note that, while this specification defines interfaces in terms of bits, octets, and frames, implementations may choose other data-path widths for implementation convenience. Supports 10-Gigabit Fibre Channel (10-GFC. Calibration 8. XGMII, as defi ned in IEEE Std 802. 3, Clause 47. Hardware and Software Requirements. XLGMII is for 40G Interface. For example, connecting either a 1000BASE-T1 PHY or a 100BASE-T1 PHY to the same RGMII or. Support to extend the IEEE 802. The MAC core along with FIFO-core and SPI4/AXI-DMA enginesUSXGMII Subsystem. (MAC) core, which can be configured in XGMII and 10GBASE-R modes. Labels: Labels: Network Management; usxgmii. - XGMII Interface (64-bit single clock edge) - POS-L3 like Interface for core logic side. 0. Reconciliation Sublayer (RS) and XGMII. ANSI TR/X3. Xilinx has 10G/25G Ethernet Subsystem IP core. e. L- and H-Tile Transceiver PHY User Guide. The inclusion of a XGMII means that several alternative PHY interfaces are readily supported, including XSBI (10 Gigabit Sixteen Bit Interface) and XAUI. Each (MAC) with a XGMII (10 Gigabit Media Independent Interface) for incorporation in a customer’s ASIC design. I would not want to retain the current electrical specification. MAC – PHY XLGMII or CGMII Interface. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. 3-2008, defines the 32-bit data and 4-bit wide control character. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User GuideIP is needed to interface the Transceiver with the XGMII compliant MAC. 1. The interface between the PCS and the RS is the XGMII as specified in Clause 46. Register Map 7. The IP supports 64-bit wide data path interface only. Session. Unidirectional. 1. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. 1 R2. 1. 3ae-2002). A 1. The XgmiiSource and XgmiiSink classes can be used to drive, receive, and monitor XGMII traffic. 1 Throughput 11 2. The data is separated into a table per device family. 6 Functional block diagraminterface. MDI – Media dependant interface. On the user side a pair of AXI4-Stream (one master and one slave) interfaces are used to send and receive Ethernet frames from/to the user logic. 1. 3125 Gbps serial single channel PHY providing a direct connection to a XFP using the XFI electrical specification or SFP\+ optical module using SFI electrical specification. Device Family Support 2. The XAUI core is an extension of the XGMII interface and as such there is no data-stripping happening within the core. The optional WAN Interface Sublayer (WIS) part of th e 10GBASE-R standard is not implemented in this core. AUTOSAR Interface. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. 3. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Download Core Submit Issue. The XGMII Controller interface block interfaces with the Data rate adaptation block. com URL: Features. 4. Avalon® -MM Interface Signals 6. 5/ commas. 20. 7. we should see DLLP packets on the interface. 49. 3 Clause 49 BASE-R physical coding sublayer/physical The 10GBASE-R PHY uses the XGMII interface to connect to the IEEE802. RGMII. 8. The system data width, that is, the width of the interface to the user logic, is c onfigured as 64 bits. 3-2008 specification. The specifications and information herein are subject to change without notice. The XGMII has an optional physical instantiation. 1. 15Introduction. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and. It utilizes built-in transceivers to implement the XAUI protocol in a single device. As I have pointed out in prior notes, a prevalent XAUI application will be as a fixed chip-to-chip interconnect not involving optical modules at all. Capacities & Specifications. XFI和SFI的来源. However there will be no change in the data when presented to the XGMII interface on the receiving end. The Universal Serial Media Independent Interface for carrying MULTIPLE network ports over a single SERDES. Arasan’s 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802. 3125 Gbps serial single channel PHY over a backplane. 145 400 Gb/s Attachment Unit Interface (400GAUI-n): A physical instantiation of the PMA service interface to extend the connection between 400 Gb/s capable PMAs over n lanes, used for chip-to-chip or chip-to-module interconnections. Avalon® -MM Interface Signals 6. 4. PHY Registers. It is now typically used for on-chip connections. At the Tampa meeting I intend to propose that we just adopt the logic family that the XGMII uses (we might have to put a note in about termination schemes as the MDIO is multi-drop). The 10GBASE-X PCS provides services to the XGMII in a manner analogous to how the 1000BASE-X PCS provides services to the 1000 Mb/s GMII. The XGMII design is now provided with the 10-Gig MAC Core in CORE Generator. xgmii mdi up to 10 gbps clt – coax line terminal cnu – coax network unit mdi – medium dependent interface oam – operations, administration, & maintenance pcs – physical coding sublayer phy – physical layer device pma – physical medium attachment pmd – physical medium dependent xgmii – gigabit media independent interfaceManagement Data Input/Output (MDIO) interface Clause 46. According to the GigE vision specification, the device registers are described in the xml file. Where possible the PIPE specification references the PCI Express base specification specification rather than repeating its content. 1. The standard XLGMII or CGMII implementation consists of 32 bit wide data bus. Features. 5M transfers/s) • PHY line rate is preserved (10. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. 3az standard for Energy Efficient Ethernet. 0 - January 2010) Agenda IEEE 802. 5GPII Word encoder/decoder –mapping between XGMII to Internal 2. PLLs and Clock Networks 4. // Documentation Portal . xgmii mdi up to 10 gbps clt – coax line terminal cnu – coax network unit mdi – medium dependent interface oam – operations, administration, & maintenance pcs – physical coding sublayer phy – physical layer device pma – physical medium attachment pmd – physical medium dependent xgmii – gigabit media independent interfaceFor D1. Several Physical Coding Sublayers known as 10GBASE-X, 10GBASE-R, and10GBASE-W are specified, as well as significant additional supporting material for a 10 GigabitMedia Independent Interface (XGMII), a 10 Gigabit Attachment. Comcores Ethernet MAC is silicon-proven and designed for easy integration into ASICs and FPGAs. Figure 46–1 shows the relationship of the RS and XGMII to the ISO/IEC (IEEE) OSI reference model. XAUI. Router with two dozen 10 Gigabit Ethernet ports and three types of physical-layer module. This is most critical for high density switches and PHY. XGMII electricals > > > > > > >In an effort to get us all on the same page, here are links to >the standard XGMII interface proposals, SSTL-2 and HSTL Class 1 >on the JEDEC site under "Free Standards":. 25MHz PCS layer XGMII interface implemented as 64-bit (single data rate) SDR interface at 156. 3 Product Guide Send Feedback 9 PG053 December 5, 2018 Chapter 2: Product Specification. Reconfiguration Signals 6. 125Gbps 10GBASE-R Clause 49 (IEEE 64B/66B PCS only) o No IEEE. Is there a reference design for for SGMII to GMII core at 2. 2 September 23, 2021 TenGEMAC IP Core Design Gateway Co. XGMII XAUI XGMII XAUI 10 Gb/s Attachment Unit Interface 4 serial lanes @ 2. The XGMII is a low-speed parallel interface for short range (approximately 2”) interconnects. Software Architecture – AUTOSAR Defined Interfaces. Figure 49–4 depicts the relationship and mapping interface. It was first defined by the IEEE 802. 11/13/2007 IEEE 802. 3ae-2002 specification requires the XAUI PHY link to support a 10 Gbps data rate at the XGMII interface and four lanes each at 3. Reduced Gigabit Media Independent Interface (RGMII) (Reduced GMII) is the most common interface as it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer. 3. 60 6. 2 Features The IP core has the following features: • 64-bit XGMII interface (MAC side) • 64-bit gearbox mode (Transceiver side) • Supported for only 64B66B PCS encoding in the transceiver • Converts the gearbox signals to the XGMII signals on the transmit interface25G-MII is a speeded up version of XGMII rather than a slowed down version of XLGMII. Designed to meet the USXGMII specification EDCS-1467841 revision 1. 11. . 5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide. 100G only has 1 data interface. The shared logic is configured to be included in the example design. The IP core is compatible with the RGMII specification v2. 3 is silent in this respect for 2. RGMII to GMII converter provides the interface between a standard gigabit media independent interface (GMII) to RGMII conversion. TOD Interface Signals. . conversion between XGMII and 2. Each direction is independent and contains a 32-bit. (MAC) with a XGMII (10 Gigabit Media Independent Interface) for incorporation in a customer’s ASIC design. That's obviously a reference to a DDR interface. . GMII TBI verification IP is developed by experts in Ethernet, who have. - Deficit Idle Count per Clause 46. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. 3. 3ae Clause 22 and Clause 45 Compliant Management Data Input / Output Interface Modes (Either 1. 3u）。介质独立的意思是指，MAC与PHY之间的通信不受具体传输介质（双绞线或光纤等）的影响，任何MAC和PHY都可以通过MII接口互连。 MAC与PHY之间的MII连接可以是可插拔的连… Interface Avalon-ST XGMII/ GMII/MII 10M/100M/ LL 10GbE MAC PHY Serial Interface Note: Intel FPGAs implement and support the LL 10GbE Media Access Control (MAC) and Multi-Rate Ethernet PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T (1G/2. 0 > 2. 4. With a mixture of 100Mbps and 1GbE nodes, system designers prefer to develop common, reusable platforms that support both types of nodes. XGMII interface in my view will be short lived. The BCM84885 is a highly integrated solution combining digital adaptive equalizers, ADCs, phase-locked loops, line drivers, encoders, decoders, echo cancelers, crosstalk cancelers, and all required support circuitry. > > 1. 0 5 Network Controller Sideband Interface (NC-SI) 6 Specification 7 Document Type: Specification 8 Document Status: DMTF Standard 9 Document Language: EThe IEEE 802. Front-Light Manager. The IP provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10. Physical. We kept the speed low to make sure that this would be a non-challenging interface. 8. 1 Power Consumption 11 2. The 10G Ethernet Verification IP is compliant with IEEE 802. > 3. OpenRAN is a project initiated by the Telecom Infra Project (TIP). Uses two transceivers at 6. A DLLP packet starts with an SDP (Start of DLLP Packet -. XGMII signaling is based on the HSTL class 1 single-ended I/O standard, which. The openapi field SHOULD be used by tooling to interpret the OpenAPI document. CAUTION: The implemented D-PHY resistor values need to be adjusted based on user design. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. 3 is used as the interface between an Ethernet physical layer device and a media access controller. 3-2012 clause 45;Support to extend the IEEE 802. 8. 3 MAC and Reconciliation Sublayer (RS). The generic nature of this interface facilitates mapping the CoaXPress signaling into the. Therefore, it is necessary to complete the conversion of GMII to XGMII interface in firmware. OSI Reference. The switch is capable of auto-negotiating with SGMII and 1000BaseX connections and by default set to SGMII. So I don't think there's an easy way to connect 100G and 25G. qua si-contract-based development. 5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor. OSI Reference model layers. 10 Gigabit Ethernet MAC The 10 Gigabit Ethernet MAC core connects to the PHY layer through an external XGMII. XAUI interoperability is based on the 10-Gigabit Ethernet standard (IEEE Standard 802. Thanks, I have this problem too. 1. This is the SDS (Start of Data Stream). 7. It utilizes built-in transceivers to implement the XAUI protocol in a single device. 2 Performance 10 2. 1for definition of SoS architectures lies in interface specification and a . Key Specifications Function Data Rate Serial I/F Parallel I/F Power Special FeaturesSGMII supports a single 10M/100M/1G network port over 1,25Gbps SERDES between MAC and PHY, while QSGMII supports four 10M/100M/1G network ports over 5Gbps SERDES between MAC and PHY. 3. Core10GMAC supports standard Ethernet interfaces such as the 10 Gbps attachment unit interface (XAUI) and the 10 Gbps reduced attachment unit interface (RXAUI). 1. It consists of pairs of Txdata, Rxdata, and Rx Ref Clk data pins. 8. 25 MHz interface clock. The IP supports 64-bit wide data path interface only. 3-2008 specification requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10. > 3. The test parameters include the part information and the core-specific configuration parameters. 0 > 2. Loading Application. © 2012 Lattice Semiconductor Corp. LightRequest. As of yet, the Task Force hasn't decided what those service interfaces look like, but I think it would be fair to assume that the PCS service interface is a 32 bit data interface and the XGXS service interface is a 4 pair differential interface (one direction only of course). Close Filter Modal. 1 XGMII Controller Interface 3. If is test the pcs/pma with 'pcs_loopback = 1' , everything works fine. There are five workstreams that comprise DC-MHS. Medium. XGMII Encapsulation 4. 3-2008 specification. ,Ltd E-mail: ip-sales@design-gateway. 3) enabled Pattern Gen code for continues sending of packet . The purpose of the QSGMII, is as you write in your own question to substitute 4 SGMII interfaces. In this demo, the FiFo_wrapper_top module provides this interface. Figure 54–1 shows the relationship of the 10GBASE-BX1 PMD sublayers and MDI to the ISO/IECThe specification requires each of the four XAUI lanes to transfer 8-bit data and 1-bit wide control code at both the positive and negative edge (DDR) of the 156. 3-2005 Clause 46) and I'm really surprised because it mentions a 32b data width for a frequency of 156. Basically, you can think of the SFP+ to BASE-T module as a media converter - it receives 10GBASE-R on one end, and produces 10GBASE-T on the other end, and vise versa. High-level overview. 4.